Latest IEEE 2026 VLSI Project Topics for MTech & BE
All topics sourced from IEEE Xplore — covering FPGA, ASIC, Low-Power VLSI, AI Accelerators, Hardware Security, RTL Design, Physical Design, STA, DFT and Emerging Semiconductor Architectures.
| # | IEEE 2026 VLSI Project Topic | Tool / Platform | Category |
|---|---|---|---|
| 01 | AI Accelerator using FPGA Architecture | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 02 | Low Power SRAM using FinFET Technology | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 03 | RISC-V Multi-Core Processor for Edge AI | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 04 | Hardware Security using Physical Unclonable Functions | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 05 | Approximate Computing DSP Processor | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 06 | Network-on-Chip for AI Workloads | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 07 | ASIC Accelerator for Transformer Models | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 08 | Ultra Low Power IoT System-on-Chip | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 09 | ECC Memory Controller Design | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 10 | 3D IC Interconnect Optimization | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 11 | Machine Learning Based Physical Design | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 12 | Low Power VLSI using Clock Gating | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 13 | FPGA Based CNN Accelerator | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 14 | Reconfigurable Computing Architecture | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 15 | High Speed UART on FPGA | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 16 | Cryptographic Processor for Secure Hardware | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 17 | Energy Efficient MAC Unit Design | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 18 | Adaptive Voltage Scaling Processor | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 19 | High Performance FFT Processor | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 20 | AI Based Fault Detection in VLSI Circuits | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 21 | Hardware Trojan Detection System | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 22 | Quantum Inspired VLSI Architecture | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 23 | FPGA Based Image Processing Engine | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 24 | Low Leakage Register File Design | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 25 | Advanced ALU for AI Applications | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 26 | ASIC Design for Autonomous Vehicles | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 27 | Neural Network Accelerator Chip | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 28 | VLSI Design for Edge Computing | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 29 | Secure RISC-V Processor Core | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 30 | Physical Design Automation using AI | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 31 | Low Power Cache Memory Architecture | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 32 | FPGA Based Speech Recognition System | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 33 | ASIC for Medical Signal Processing | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 34 | VLSI Architecture for Smart Sensors | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 35 | 5G Baseband Processor Design | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 36 | Digital Predistortion Accelerator | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 37 | High Speed PCIe Controller | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 38 | On-Chip Power Management Unit | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 39 | Low Power Arithmetic Logic Unit | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 40 | Hardware Accelerator for Deep Learning | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 41 | FPGA Based Video Analytics Engine | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 42 | ASIC Based Object Detection Processor | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 43 | High Throughput AES Encryption Engine | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 44 | Low Power NoC Architecture | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 45 | Memory Built-In Self-Test Design | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 46 | VLSI Based Biomedical Signal Processor | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 47 | High Speed Multiplier Architecture | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 48 | FPGA Based Radar Signal Processor | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 49 | ASIC Based Edge AI Processor | Cadence / Xilinx Vivado | IEEE 2026 VLSI |
| 50 | Next Generation Semiconductor IP Core | Cadence / Xilinx Vivado | IEEE 2026 VLSI |